System and Method to Provide Persistent Storage Class Memory using NVDIMM-N with an NVDIMM-P Footprint

ABSTRACT

A non-volatile dual in-line memory module (NVDIMM) includes a dynamic random access memory (DRAM) block, a plurality of non-volatile random access memory (NVRAM) blocks, and an NVDIMM controller. The DRAM block is organized into a number (N) of pages. Each NVRAM block is organized into the number (N) of pages, each page of the DRAM block being N-way set associatively associated with a page of each of the NVRAM blocks. The NVDIMM controller is configured to copy first data from a first page of a first NVRAM block to an associated first page of the DRAM block.

FIELD OF THE DISCLOSURE

This disclosure generally relates to information handling systems, andmore particularly relates to providing persistent storage class memoryusing NVDIMM-N with an NVDIMM-P footprint.

BACKGROUND

As the value and use of information continues to increase, individualsand businesses seek additional ways to process and store information.One option is an information handling system. An information handlingsystem generally processes, compiles, stores, and/or communicatesinformation or data for business, personal, or other purposes. Becausetechnology and information handling needs and requirements may varybetween different applications, information handling systems may alsovary regarding what information is handled, how the information ishandled, how much information is processed, stored, or communicated, andhow quickly and efficiently the information may be processed, stored, orcommunicated. The variations in information handling systems allow forinformation handling systems to be general or configured for a specificuser or specific use such as financial transaction processing,reservations, enterprise data storage, or global communications. Inaddition, information handling systems may include a variety of hardwareand software resources that may be configured to process, store, andcommunicate information and may include one or more computer systems,data storage systems, and networking systems.

SUMMARY

A non-volatile dual in-line memory module (NVDIMM) may include a dynamicrandom access memory (DRAM) block, a plurality of non-volatile randomaccess memory (NVRAM) blocks, and an NVDIMM controller. The DRAM blockmay be organized into a number (N) of pages. Each NVRAM block may beorganized into the number (N) of pages, each page of the DRAM blockbeing N-way set associatively associated with a page of each of theNVRAM blocks. The NVDIMM controller may be configured to copy first datafrom a first page of a first NVRAM block to an associated first page ofthe DRAM block.

BRIEF DESCRIPTION OF THE DRAWINGS

It will be appreciated that for simplicity and clarity of illustration,elements illustrated in the Figures have not necessarily been drawn toscale. For example, the dimensions of some of the elements areexaggerated relative to other elements. Embodiments incorporatingteachings of the present disclosure are shown and described with respectto the drawings presented herein, in which:

FIG. 1 is a block diagram illustrating a generalized informationhandling system according to an embodiment of the present disclosure;

FIG. 2 is a block diagram illustrating an information handling systemincluding a memory controller and an NVDIMM according to an embodimentof the present disclosure;

FIG. 3 illustrates the information handling system of FIG. 2 with anexemplary data storage configuration;

FIG. 4 illustrates a method of accessing data stored in the NVDIMM ofFIG. 2, according to an embodiment of the present disclosure; and

FIG. 5 illustrates a method of accessing data stored in the NVDIMM ofFIG. 2, according to another embodiment of the present disclosure.

The use of the same reference symbols in different drawings indicatessimilar or identical items.

DETAILED DESCRIPTION OF DRAWINGS

The following description in combination with the Figures is provided toassist in understanding the teachings disclosed herein. The followingdiscussion will focus on specific implementations and embodiments of theteachings. This focus is provided to assist in describing the teachings,and should not be interpreted as a limitation on the scope orapplicability of the teachings. However, other teachings can certainlybe used in this application. The teachings can also be used in otherapplications, and with several different types of architectures, such asdistributed computing architectures, client/server architectures, ormiddleware server architectures and associated resources.

FIG. 1 illustrates a generalized embodiment of an information handlingsystem 100. For purpose of this disclosure information handling system100 can be configured to provide the features and to perform thefunctions of the OPF system as described herein. Information handlingsystem 100 can include any instrumentality or aggregate ofinstrumentalities operable to compute, classify, process, transmit,receive, retrieve, originate, switch, store, display, manifest, detect,record, reproduce, handle, or utilize any form of information,intelligence, or data for business, scientific, control, entertainment,or other purposes. For example, information handling system 100 can be apersonal computer, a laptop computer, a smart phone, a tablet device orother consumer electronic device, a network server, a network storagedevice, a switch router or other network communication device, or anyother suitable device and may vary in size, shape, performance,functionality, and price. Further, information handling system 100 caninclude processing resources for executing machine-executable code, suchas a central processing unit (CPU), a programmable logic array (PLA), anembedded device such as a System-on-a-Chip (SoC), or other control logichardware. Information handling system 100 can also include one or morecomputer-readable medium for storing machine-executable code, such assoftware or data. Additional components of information handling system100 can include one or more storage devices that can storemachine-executable code, one or more communications ports forcommunicating with external devices, and various input and output (I/O)devices, such as a keyboard, a mouse, and a video display. Informationhandling system 100 can also include one or more buses operable totransmit information between the various hardware components.

Information handling system 100 can include devices or modules thatembody one or more of the devices or modules described below, andoperates to perform one or more of the methods described below.Information handling system 100 includes a processors 102 and 104, achipset 110, a memory 120, a graphics interface 130, a basic input andoutput system/universal extensible firmware interface (BIOS/UEFI) module140, a disk controller 150, a hard disk drive (HDD) 154, an optical diskdrive (ODD) 156, a disk emulator 160 connected to an external solidstate drive (SSD) 162, an input/output (I/O) interface 170, one or moreadd-on resources 174, a trusted platform module (TPM) 176, a networkinterface 180, a management block 190, and a power supply 195.Processors 102 and 104, chipset 110, memory 120, graphics interface 130,BIOS/UEFI module 140, disk controller 150, HDD 154, ODD 156, diskemulator 160, SSD 162, I/O interface 170, add-on resources 174, TPM 176,and network interface 180 operate together to provide a host environmentof information handling system 100 that operates to provide the dataprocessing functionality of the information handling system. The hostenvironment operates to execute machine-executable code, includingplatform BIOS/UEFI code, device firmware, operating system code,applications, programs, and the like, to perform the data processingtasks associated with information handling system 100.

In the host environment, processor 102 is connected to chipset 110 viaprocessor interface 106, and processor 104 is connected to the chipsetvia processor interface 108. Memory 120 is connected to chipset 110 viaa memory bus 122. Graphics interface 130 is connected to chipset 110 viaa graphics interface 132, and provides a video display output 136 to avideo display 134. In a particular embodiment, information handlingsystem 100 includes separate memories that are dedicated to each ofprocessors 102 and 104 via separate memory interfaces. An example ofmemory 120 includes random access memory (RAM) such as static RAM(SRAM), dynamic RAM (DRAM), non-volatile RAM (NV-RAM), or the like, readonly memory (ROM), another type of memory, or a combination thereof.

BIOS/UEFI module 140, disk controller 150, and I/0 interface 170 areconnected to chipset 110 via an I/O channel 112. An example of I/Ochannel 112 includes a Peripheral Component Interconnect (PCI)interface, a PCI-Extended (PCI-X) interface, a high speed PCI-Express(PCIe) interface, another industry standard or proprietary communicationinterface, or a combination thereof. Chipset 110 can also include one ormore other I/O interfaces, including an Industry Standard Architecture(ISA) interface, a Small Computer Serial Interface (SCSI) interface, anInter-Integrated Circuit (I²C) interface, a System Packet Interface(SPI), a Universal Serial Bus (USB), another interface, or a combinationthereof. BIOS/UEFI module 140 includes BIOS/UEFI code operable to detectresources within information handling system 100, to provide drivers forthe resources, initialize the resources, and access the resources.BIOS/UEFI module 140 includes code that operates to detect resourceswithin information handling system 100, to provide drivers for theresources, to initialize the resources, and to access the resources.

Disk controller 150 includes a disk interface 152 that connects the diskcontroller to HDD 154, to ODD 156, and to disk emulator 160. An exampleof disk interface 152 includes an Integrated Drive Electronics (IDE)interface, an Advanced Technology Attachment (ATA) such as a parallelATA (PATA) interface or a serial ATA (SATA) interface, a SCSI interface,a USB interface, a proprietary interface, or a combination thereof. Diskemulator 160 permits SSD 164 to be connected to information handlingsystem 100 via an external interface 162. An example of externalinterface 162 includes a USB interface, an IEEE 1394 (Firewire)interface, a proprietary interface, or a combination thereof.Alternatively, solid-state drive 164 can be disposed within informationhandling system 100.

I/O interface 170 includes a peripheral interface 172 that connects theI/O interface to add-on resource 174, to TPM 176, and to networkinterface 180. Peripheral interface 172 can be the same type ofinterface as I/O channel 112, or can be a different type of interface.As such, I/O interface 170 extends the capacity of I/O channel 112 whenperipheral interface 172 and the I/O channel are of the same type, andthe I/O interface translates information from a format suitable to theI/O channel to a format suitable to the peripheral channel 172 when theyare of a different type. Add-on resource 174 can include a data storagesystem, an additional graphics interface, a network interface card(NIC), a sound/video processing card, another add-on resource, or acombination thereof. Add-on resource 174 can be on a main circuit board,on separate circuit board or add-in card disposed within informationhandling system 100, a device that is external to the informationhandling system, or a combination thereof.

Network interface 180 represents a NIC disposed within informationhandling system 100, on a main circuit board of the information handlingsystem, integrated onto another component such as chipset 110, inanother suitable location, or a combination thereof. Network interfacedevice 180 includes network channels 182 and 184 that provide interfacesto devices that are external to information handling system 100. In aparticular embodiment, network channels 182 and 184 are of a differenttype than peripheral channel 172 and network interface 180 translatesinformation from a format suitable to the peripheral channel to a formatsuitable to external devices. An example of network channels 182 and 184includes InfiniBand channels, Fibre Channel channels, Gigabit Ethernetchannels, proprietary channel architectures, or a combination thereof.Network channels 182 and 184 can be connected to external networkresources (not illustrated). The network resource can include anotherinformation handling system, a data storage system, another network, agrid management system, another suitable resource, or a combinationthereof.

Management block 190 represents one or more processing devices, such asa dedicated baseboard management controller (BMC) System-on-a-Chip (SoC)device, one or more associated memory devices, one or more networkinterface devices, a complex programmable logic device (CPLD), and thelike, that operate together to provide the management environment forinformation handling system 100. In particular, management block 190 isconnected to various components of the host environment via variousinternal communication interfaces, such as a Low Pin Count (LPC)interface, an Inter-Integrated-Circuit (I2C) interface, a PCIeinterface, or the like, to provide an out-of-band (OOB) mechanism toretrieve information related to the operation of the host environment,to provide BIOS/UEFI or system firmware updates, to managenon-processing components of information handling system 100, such assystem cooling fans and power supplies. Management block 190 can includea network connection to an external management system, and themanagement block can communicate with the management system to reportstatus information for information handling system 100, to receiveBIOS/UEFI or system firmware updates, or to perform other task formanaging and controlling the operation of information handling system100. Management block 190 can operate off of a separate power plane fromthe components of the host environment so that the management blockreceives power to manage information handling system 100 when theinformation handling system is otherwise shut down. An example ofmanagement block 190 may include a commercially available BMC productthat operates in accordance with an Intelligent Platform ManagementInitiative (IPMI) specification, such as a Integrated Dell Remote AccessController (iDRAC), or the like. Management block 190 may furtherinclude associated memory devices, logic devices, security devices, orthe like, as needed or desired.

Power supply 195 represents one or more devices for power distributionto the components of information handling system 100. In particular,power supply 195 can include a main power supply that receives powerfrom an input power source, such as a wall power outlet, a power strip,a battery, or another power source, as needed or desired. Here, powersource 195 operates to convert the power at a first voltage level fromthe input power source to one or more power rails that are utilized bythe components of information handling system. Power supply 195 can alsoinclude one or more voltage regulators (VRs) that each receive powerfrom the main power supply and that operate to convert the input voltageto an output voltage that is used by one or more components ofinformation handling system. For example, a VR can be provided for eachof processors 102 and 104, and another VR can be provided for memory120. Power supply 195 can be configured to provide a first power planethat provides power to the host environment, and to provide a secondpower plane that provides power to the management environment.

FIG. 2 illustrates an information handling system 200 similar toinformation handling system 100, including a processor complex 210 and anon-volatile dual in-line memory module (NVDIMM) 220. Processor complex210 operates to provide data processing functionality of informationhandling system 200, such as is typically associated with an informationhandling system. As such, processor complex 210 represents a dataprocessing apparatus, such as one or more central processing units(CPUs) or processor cores, and the associated data input and output I/Ofunctionality, such as a chipset component, and other I/O processorcomponents. Processor complex 210 operates to execute machine-executablecode to perform the data processing tasks associated with informationhandling system 200.

Memory controller 212 represents a portion of the processor complex thatis dedicated to the management of the data storage and retrieval fromthe memory devices of information handling system 200, and informationhandling system 200 may include one or more additional memorycontrollers similar to memory controller 212, as needed or desired.Memory controller 212 may reside on a system printed circuit board, maybe integrated into an I/O processor component, may be integrated with aprocessor on a system-on-a-chip (SoC), or may be implemented in anotherway, as needed or desired. Memory controller 212 operates to providedata and control interfaces to one or more DIMM, such as NVDIMM 220 inaccordance with a particular memory architecture. For example, memorycontroller 212 and NVDIMM 220 may operate in accordance with aDouble-Data Rate (DDR) standard, such as a JEDEC DDR4 or DDR5 standard.

NVDIMM 220 represents a memory device of information handling system 200that is packaged as a DIMM in accordance with the particular memoryarchitecture by which memory controller 212 operates. NVDIMM 220includes an NVDIMM controller 222, a dynamic random access memory (DRAM)block 230, and non-volatile random access memory (NVRAM) blocks 240,250, 260, and 270. DRAM block 230 represents one or more DRAM devicesand NVRAM blocks 240, 250, 260, and 270 each represent one or more NVRAMdevices.

It will be understood by the skilled artisan, that NVRAM blocks 240,250, 260, and 270 may provide a large data storage capacity, as comparedto DRAM block 230, but with a substantially longer data access latency.On the other hand, it will be understood that DRAM block 230 may providea smaller data storage capacity, but with a much shorter data accesslatency. Further, the skilled artisan will understand that DRAM block230 may provide byte-addressable data access, while NVRAM blocks 240,250, 260, and 270 may typically be block-addressable. For example, atypical DRAM DIMM may provide a data storage capacity of 32 gigabytes(GB), 64 GB, 128 GB, or more, with access latencies around 10+nanoseconds (ns), while a typical NVDIMM-P may provide a data storagecapacity of 100 GB to 1 terabyte (TB), with access latencies around 100+ns. As described further below, NVDIMM 220 operates to provide a largedata storage capacity, as determined by the combined data storagecapacities of NVRAM blocks 240, 250, 260, and 270, but withbyte-addressability and low data access latency as provided by DRAMblock 230.

Memory controller 212 operates to byte-addressably map the entire memoryspace of the combined data storage capacities of NVRAM blocks 240, 250,260, and 270, such that memory transactions targeted to any bytelocation of the NVRAM blocks can be accessed by paging the informationfrom the NVRAM blocks into DRAM block 230, and then accessing the datafrom the byte location directly from the DRAM block. As such, DRAM block230 is organized into pages 232. For example, where DRAM block 230represents a 32 GB DRAM memory, the DRAM block can be organized intofour pages of 8 GB each, into eight pages of 4 GB each, into 16 pages of2 GB each, or into another number of pages, as needed or desired.Similarly, NVRAM blocks 240, 250, 260, and 270 are each organized intorespective pages 242, 252, 262, and 272, where the NVRAM blocks eachinclude the same number of pages as DRAM block 230.

In operation, pages 232 are n-way set associatively mapped to pages 242,252, 262, and 272 such that selected pages from NVRAM blocks 240, 250,260, and 270 are copied into associated pages 232. For example, whereeach of DRAM block 230 and NVRAM blocks 240, 250, 260, and 270 includefour pages, then the first page (page 0) of any one of pages 242, 252,262, and 272 can be stored at the first page (page 0) of pages 232, thesecond page (page 1) of any one of pages 242, 252, 262, and 272 can bestored at the second page (page 1) of pages 232, and etc. Then, whenmemory controller 212 makes a memory access to a byte address within apage that is copied into one of pages 232, the memory transaction isserviced by DRAM block 230 directly. On the other hand, when memorycontroller 212 makes a memory access to a byte address within a pagethat is not copied into one of pages 232, then the memory controllerdirects NVDIMM controller 222 to evict the particular copied page ofpages 232 back to the source page of pages 242, 252, 262, or 272, and tocopy the addressed page of pages 242, 252, 262, or 272 into theassociated page of pages 232, before servicing the memory accessdirectly from DRAM block 230.

To manage the operations of NVDIMM 220, memory controller 212 includes apage table 214 that maintains information as to the current state ofDRAM block 230. As such, page table 214 includes a number of page tableentries 216 that is equal to the number of pages 232, 242, 252, 262, and272. Here, where each of DRAM block 230 and NVRAM blocks 240, 250, 260,and 270 include four pages, a first page table entry (page 0) isassociated with the first page table entries (page 0) of the DRAM blockand the NVRAM blocks, a second page table entry (page 1) is associatedwith the second page table entries (page 1) of the DRAM block and theNVRAM blocks, and etc. Thus each page table entry 216 is associated witha page, and includes an identifier of the NVRAM block 240, 250, 260, and270 that is currently copied into the associated page 232 of DRAM block230. Each page table entry 216 includes a valid bit to identify whetheror not the currently mapped entry of the page table entries is valid,that is, that the page table entry correctly identifies which page 242,252, 262, or 272 is currently copied to page 232.

Thus, when processor complex 210 issues a memory transaction, memorycontroller 212 first checks page table 214 to determine if the byteaddress of the memory transaction is associated with a page 242, 252,262, or 272, that is currently copied into DRAM block 230. Here, memorycontroller 212 first determines that the byte address is within thememory range one of NVRAM blocks 240, 250, 260, and 270, and is within aparticular page (page 0, page 1, page 2, or page 3) of pages 242, 252,262, or 272 of that NVRAM block. Then, having identified the NVRAM block240, 250, 260, or 270 and the particular page (page 0, page 1, page 2,or page 3), memory controller 212 checks the associated page table entry(entry 0, entry 1, entry 2, or entry 3) of page table entries 216 todetermine if the identified NVRAM block is indicated as being copied tothe associated page (page 0, page 1, page 2, or page 3) of pages 232,and if the indication is valid.

If the check indicates that the memory transaction is to a page that iscopied to DRAM block 230, then memory controller 212 issues thetransaction on the command/address bus to NVDIMM controller 222, andperforms the memory transaction on the data bus with the DRAM block.However, if the check indicates that the memory transaction is not to apage that is copied to DRAM block 230, then memory controller 212 sendsa swap page command to NVDIMM controller 222 on the command/address busdirecting the NVDIMM controller to evict the particular copied page ofpages 232 back to the source page of pages 242, 252, 262, or 272, and tocopy the addressed page of pages 242, 252, 262, or 272 into theassociated page of pages 232.

In a particular embodiment, when the memory transaction is not to a pagethat is copied to DRAM block 230, memory controller 212 also places thememory transaction into a hold until NVDIMM controller 222 provides anindication that the swap page command has been executed. Then memorycontroller 212 issues the memory transaction on the command/address busto NVDIMM controller 222, and performs the memory transaction on thedata bus with DRAM block 230. An example of the indication can include adedicated signal line between memory controller 212 and NVDIMMcontroller 222, an assertion by the NVDIMM controller of an ALERT_Nsignal which prompts the memory controller to perform a service routineto discover that the swap is complete, or another indication. Where theindication is via the assertion of the ALERT_N signal, NVDIMM controller222 can store status information related to the swap page command inregister space of the NVDIMM controller to identify the type ofindication.

In another embodiment, the swap page command also includes the memorytransaction. Here, when NVDIMM controller 222 has executed the swap pagecommand, then the memory transaction is also performed on the data buswith DRAM block 230, without having to receive a separate memorytransaction from memory controller 212. Here, the duration of time formemory controller 222 to evict the particular copied page of pages 232back to the source page of pages 242, 252, 262, or 272, and to copy theaddressed page of pages 242, 252, 262, or 272 into the associated pageof pages 232 can be a fixed duration. As such, memory controller 212 isconfigured to expect the reply to the memory transaction after the fixedduration. In a particular case, NVDIMM controller 222 can include theduration in the Serial Presence Detect (SPD) information that isdiscovered by memory controller 212 during memory initialization.

NVDIMM controller 222 is illustrated as including a page table 224similar to page table 214, and including page table entries 226 similarto page table entries 216. Here, NVDIMM controller 222 will maintainpage table 224 to mirror the contents of page table 214, and when memorycontroller 212 issues a swap page command, the NVDIMM controller willalso update page table entries 226 to maintain consistency between thepage tables.

It will be understood that DRAM block 230 consist of one or more DRAMdevices. Moreover, where DRAM block 230 consists of more than one DRAMdevice, pages 232 may span across more than one DRAM device, or man bydefined wholly within a single DRAM device, as needed or desired.Further, it will be understood that NVRAM blocks 240, 250, 260, and 270may consist of a single NVRAM device or may consist of more than onedevice. For example, where NVRAM blocks 240, 250, 260, and 270 consistof a single NVRAM device, the NVRAM device may be organized such thatdifferent memory portions of the NVRAM device are organized into thevarious NVRAM blocks, and in general, a single NVRAM device may beorganized as all or parts of multiple NVRAM blocks. In another example,where NVRAM blocks 240, 250, 260, and 270 consist of four NVRAM devices,each NVRAM device may be associated with a single NVRAM block, or theNVRAM blocks may each span across multiple NVRAM devices.

FIG. 3 illustrates information handling system 200 with an exemplarydata storage configuration in NVDIMM 220. Here, the first page (page 0)of pages 232 stores a copy of the first page (page 0) of NVRAM block 240(block 00), the second page (page 1) of pages 232 stores a copy of thesecond page (page 1) of NVRAM block 250 (block 01), the third page (page2) of pages 232 stores a copy of the third page (page 2) of NVRAM block260 (block 10), and the fourth page (page 3) of pages 232 stores a copyof the fourth page (page 3) of NVRAM block 270 (block 11). Reflectingthis data storage configuration, the first page table entry (entry 0) ofpage table 214 shows that the first page (page 0) of pages 232 storesthe first page (page 0) of NVRAM block 240 (block 00) and is valid, thesecond page table entry (entry 1) shows that the second page (page 1) ofpages 232 stores the second page (page 1) of NVRAM block 250 (block 01)and is valid, the third page table entry (entry 2) shows that the thirdpage (page 2) of pages 232 stores the third page (page 2) of NVRAM block260 (block 10) and is valid, and the fourth page table entry (entry 3)shows that the fourth page (page 3) of pages 232 stores the fourth page(page 3) of NVRAM block 270 (block 11) and is valid. Finally, page table224 reflects the information of page table 214.

FIG. 4 illustrates a method of accessing data stored in an NVRAM block240, 250, or 260 that is not resident in DRAM block 230. FIG. 4 assumesan initial condition as found in FIG. 3, above. A memory transaction isreceived from processor complex 210 by memory controller 212 in step402. Memory transaction 402 is for a byte address in page 3 of block 00.Memory controller 212 checks whether or not page 3 of block 00 is copiedto page 3 of DRAM block 230 in entry 3 of page table 214. Memorycontroller 212 discovers that entry 3 of page table 214 indicates thatpage 3 of NVRAM block 270 (block 11) is copied to page 3 of DRAM block230. In response, memory controller 212 holds the memory transactionfrom step 402 and issues a swap page command to NVDIMM controller 222,directing the NVDIMM controller to swap page 3 in DRAM block 230, thatis, the page 3 data of NVRAM block 270 (block 11), with the page 3 dataof NVRAM block 240 (block 00) in step 404.

In response to receiving the swap page command in step 404, NVDIMMcontroller 222 directs a write-back of the page 3 data from DRAM block230 to page 3 of NVRAM 270 (block 11) in step 406, and directs a dataretrieval of the page 3 data from NVRAM 240 (block 00) to page 3 of DRAMblock 230 in step 408. NVDIMM controller 222 then updates entry 3 ofpage table 226 to reflect that page 3 of DRAM block 230 now stores acopy of the page 3 data of NBRAM block 240 in step 410, and sends aresponse to memory controller 212 that the page swap command has beenexecuted in step 412. Memory controller 212 then updates entry 3 of pagetable 212 to indicate that page 3 of DRAM block 230 now stores a copy ofthe page 3 data of NBRAM block 240 in step 414. Finally, memorycontroller 212 issues the memory transaction to page 3 of block 00 toNVDIMM controller 222 in block 416, and performs the memory transactionwith page 3 of DRAM block 230 in step 418.

FIG. 5 illustrates another method of accessing data stored in an NVRAMblock 240, 250, or 260 that is not resident in DRAM block 230. FIG. 5assumes an initial condition as found in FIG. 3, above. A memorytransaction is received from processor complex 210 by memory controller212 in step 502. Memory transaction 502 is for a byte address in page 3of block 00. Memory controller 212 checks whether or not page 3 of block00 is copied to page 3 of DRAM block 230 in entry 3 of page table 214.Memory controller 212 discovers that entry 3 of page table 214 indicatesthat page 3 of NVRAM block 270 (block 11) is copied to page 3 of DRAMblock 230. In response, memory controller 212 issues a swap page commandto NVDIMM controller 222, directing the NVDIMM controller to swap page 3in DRAM block 230, that is, the page 3 data of NVRAM block 270 (block11), with the page 3 data of NVRAM block 240 (block 00) in step 504. Theswap page command in step 504 also includes the memory transaction fromstep 502.

In response to receiving the swap page command/memory transaction instep 504, NVDIMM controller 222 holds the memory transaction, directs awrite-back of the page 3 data from DRAM block 230 to page 3 of NVRAM 270(block 11) in step 506, and directs a data retrieval of the page 3 datafrom NVRAM 240 (block 00) to page 3 of DRAM block 230 in step 508.NVDIMM controller 222 then updates entry 3 of page table 226 to reflectthat page 3 of DRAM block 230 now stores a copy of the page 3 data ofNBRAM block 240 in step 510, and executes the memory transaction withpage 3 of DRAM block 230 in step 512. Memory controller 212 then updatesentry 3 of page table 212 to indicate that page 3 of DRAM block 230 nowstores a copy of the page 3 data of NBRAM block 240 in step 514.

Although only a few exemplary embodiments have been described in detailherein, those skilled in the art will readily appreciate that manymodifications are possible in the exemplary embodiments withoutmaterially departing from the novel teachings and advantages of theembodiments of the present disclosure. Accordingly, all suchmodifications are intended to be included within the scope of theembodiments of the present disclosure as defined in the followingclaims. In the claims, means-plus-function clauses are intended to coverthe structures described herein as performing the recited function andnot only structural equivalents, but also equivalent structures.

The above-disclosed subject matter is to be considered illustrative, andnot restrictive, and the appended claims are intended to cover any andall such modifications, enhancements, and other embodiments that fallwithin the scope of the present invention. Thus, to the maximum extentallowed by law, the scope of the present invention is to be determinedby the broadest permissible interpretation of the following claims andtheir equivalents, and shall not be restricted or limited by theforegoing detailed description.

What is claimed is:
 1. A non-volatile dual in-line memory module(NVDIMM), comprising: a dynamic random access memory (DRAM) block, theDRAM block organized into a number (N) of pages; a plurality ofnon-volatile random access memory (NVRAM) blocks, each NVRAM blockorganized into the number (N) of pages, each page of the DRAM blockbeing N-way set associatively associated with a page of each of theNVRAM blocks; and an NVDIMM controller configured to copy first datafrom a first page of a first NVRAM block to an associated first page ofthe DRAM block.
 2. The NVDIMM of claim 1, the NVDIMM configured torespond to a first memory transaction targeted to a first address withinthe first page of the first NVRAM block from the associated first pageof the DRAM block.
 3. The NVDIMM of claim 2, the NVDIMM controllerconfigured to receive the first memory transaction from a memorycontroller.
 4. The NVDIMM of claim 3, wherein the NVDIMM controller isconfigured, prior to receiving the first memory transaction, to: receivea page swap command from the memory controller, the page swap commandidentifying a first page of a second NVRAM block previously copied tothe first page of the DRAM block and identifying the first page of thefirst NVRAM block; and copy second data from the first page of the DRAMblock to the first page of the second NVRAM block in response toreceiving the page swap command.
 5. The NVDIMM of claim 4, wherein:copying the first data from the first page of the first NVRAM block tothe first page of the DRAM block is in further response to receiving thepage swap command and is done after the second data is copied from thefirst page of the DRAM block to the first page of the second NVRAMblock; the NVDIMM controller is further configured to send a reply tothe memory controller that the swap page command has been executed inresponse to copying the first data from the first page of the firstNVRAM block to the first page of the DRAM block.
 6. The NVDIMM of claim3, the NVDIMM controller further configured to: receive a second memorytransaction from the memory controller, the second memory transactiontargeted to a second address within a first page of a second NVRAMblock, the first page of the second NVRAM block associated with thefirst page of the DRAM block; copy the first data from the first page ofthe DRAM block to the first page of the first NVRAM block in response toreceiving the second memory transaction; and copy second data from thefirst page of the second NVRAM block to the first page of the DRAM blockin further response to receiving the second memory transaction.
 7. TheNVDIMM of claim 6, the NVDIMM configured to respond to the second memorytransaction from the first page of the DRAM block after the second datafrom the first page of the second NVRAM block is copied to the firstpage of the DRAM block.
 8. The NVDIMM of claim 3, wherein the NVDIMMcontroller copies the first data from the first page of the first NVRAMblock to the associated first page of the DRAM block in response toreceiving the first memory transaction.
 9. A method, comprising:organizing a dynamic random access memory (DRAM) block of a non-volatiledual in-line memory module (NVDIMM) into a number (N) of pages;organizing each non-volatile random access memory (NVRAM) block of aplurality of NVRAM blocks of the NVDIMM into the number (N) of pages,each page of the DRAM block being N-way set associatively associatedwith a page of each of the NVRAM blocks; and copying, by an NVDIMMcontroller of the NVDIMM, first data from a first page of a first NVRAMblock to an associated first page of the DRAM block.
 10. The method ofclaim 9, further comprising: responding, by the NVDIMM, to respond to afirst memory transaction targeted to a first address within the firstpage of the first NVRAM block from the associated first page of the DRAMblock.
 11. The method of claim 10, further comprising: receiving, by theNVDIMM controller, the first memory transaction from a memorycontroller.
 12. The method of claim 11, further comprising, prior toreceiving the first memory transaction: receiving, by the NVDIMMcontroller, a page swap command from the memory controller, the pageswap command identifying a first page of a second NVRAM block previouslycopied to the first page of the DRAM block and identifying the firstpage of the first NVRAM block; and copying, by the NVDIMM controller,second data from the first page of the DRAM block to the first page ofthe second NVRAM block in response to receiving the page swap command.13. The method of claim 12, wherein: copying the first data from thefirst page of the first NVRAM block to the first page of the DRAM blockis in further response to receiving the page swap command and is doneafter the second data is copied from the first page of the DRAM block tothe first page of the second NVRAM block; the method further comprisingsending, by the NVDIMM controller, a reply to the memory controller thatthe swap page command has been executed in response to copying the firstdata from the first page of the first NVRAM block to the first page ofthe DRAM block.
 14. The method of claim 11, further comprising:receiving, by the NVDIMM controller, a second memory transaction fromthe memory controller, the second memory transaction targeted to asecond address within a first page of a second NVRAM block, the firstpage of the second NVRAM block associated with the first page of theDRAM block; copying, by the NVDIMM controller, the first data from thefirst page of the DRAM block to the first page of the first NVRAM blockin response to receiving the second memory transaction; and copying, bythe NVDIMM controller, second data from the first page of the secondNVRAM block to the first page of the DRAM block in further response toreceiving the second memory transaction.
 15. The method of claim 14,further comprising: responding, by the NVDIMM, to the second memorytransaction from the first page of the DRAM block after the second datafrom the first page of the second NVRAM block is copied to the firstpage of the DRAM block.
 16. The method of claim 11, wherein the NVDIMMcontroller copies the first data from the first page of the first NVRAMblock to the associated first page of the DRAM block in response toreceiving the first memory transaction.
 17. An information handlingsystem, comprising: a memory controller; and a non-volatile dual in-linememory module (NVDIMM) including: a dynamic random access memory (DRAM)block, the DRAM block organized into a number (N) of pages; a pluralityof non-volatile random access memory (NVRAM) blocks, each NVRAM blockorganized into the number (N) of pages, each page of the DRAM blockbeing N-way set associatively associated with a page of each of theNVRAM blocks; and an NVDIMM controller configured to copy first datafrom a first page of a first NVRAM block to an associated first page ofthe DRAM block; wherein the memory controller is configured to send afirst memory transaction targeted to a first address within the firstpage of the first NVRAM block to the NVDIMM controller, and the NVDIMMis configured to respond to the first memory transaction from theassociated first page of the DRAM block.
 18. The information handlingsystem of claim 17, the NVDIMM controller further configured to receivethe first memory transaction from a memory controller.
 19. Theinformation handling system of claim 18, wherein the NVDIMM controlleris configured, prior to receiving the first memory transaction, to:receive a page swap command from the memory controller, the page swapcommand identifying a first page of a second NVRAM block previouslycopied to the first page of the DRAM block and identifying the firstpage of the first NVRAM block; and copy second data from the first pageof the DRAM block to the first page of the second NVRAM block inresponse to receiving the page swap command.
 20. The informationhandling system of claim 19, wherein: copying the first data from thefirst page of the first NVRAM block to the first page of the DRAM blockis in further response to receiving the page swap command and is doneafter the second data is copied from the first page of the DRAM block tothe first page of the second NVRAM block; the NVDIMM controller isfurther configured to send a reply to the memory controller that theswap page command has been executed in response to copying the firstdata from the first page of the first NVRAM block to the first page ofthe DRAM block.